Unified multifunctional-reconfigurable architecture for device-circuit co-design

Abstract

In this article, we propose a novel unified device-circuit co-design for functional scalability and diversifiability within the same footprint. The proposed design comprises two L-shaped NMOS monolithically integrated with two L-shaped PMOS utilizing common silicon reservoir with charge-plasma (CP) induced source and drain regions. The CP regions are induced by choosing appropriate work functions for the metal electrodes using calibrated TCAD simulations. Through source-drain interchangeability among individual transistors and appropriate signal bias, we have demonstrated the possible reconfigurations of the proposed single architecture to perform various device and/or circuit level operations concurrently/separately. For device level analyses, we realized concurrent NMOS and PMOS in single-channel and/or dual-channel configurations. Further, for circuit level analyses, we realized a CMOS inverter in addition to an NMOS and a PMOS, all three operating independently. Next, we demonstrated two independent inverters with possible realization of a buffer. Lastly, we present NAND and NOR Gates, each in two possible configurations, obtained through the proposed single-device architecture.