3 - NAND and NOR logic

Abstract

This chapter provides an overview of NAND and NOR gates of Boolean algebra. In practice, many logic circuits are implemented using NAND and NOR gates simply because the basic gates in some logic families, such as transistor–transistor logic and complementary metal-oxide semiconductor, are NAND and NOR gates. It is true that the AND and OR gates exist in these families, but there is a very much smaller selection of them and they are usually more expensive. The AND and OR gates in these families usually have longer delay times because they have more stages than the NAND and NOR gates and they may also have a higher power dissipation. The NAND function is defined by the Boolean equation, ▪. The implementation of the AND function using NAND gates is simply performed by connecting two NAND gates in the cascade, the first one performing the NAND operation while the second one is used as an inverter. The technique for the implementation of a Boolean function using NAND gates does not necessarily lead to the minimal NAND implementation. However, sometimes by using a factorization process, it is a simple matter to produce a NAND implementation that leads to a circuit that requires a smaller number of gates. The Zissos method is a systematic way of determining the effect of merging on the number of gates required for the NAND implementation of a given function.