Abstract
Perpendicular magnetic tunnel junctions (MTJ) with a bottom pinned reference layer and a composite free layer (FL) are investigated. Different thicknesses of the FL were tested to obtain an optimal balance between tunneling magnetoresistance (TMR) ratio and perpendicular magnetic anisotropy. After annealing at 400 °C, the TMR ratio for 1.5 nm thick CoFeB sublayer reached 180% at room temperature and 280% at 20 K with an MgO tunnel barrier thickness corresponding to the resistance area product RA = 10 Ohmμm2. The voltage vs. magnetic field stability diagrams measured in pillar-shaped MTJs with 130 nm diameter indicate the competition between spin transfer torque (STT), voltage controlled magnetic anisotropy (VCMA) and temperature effects in the switching process. An extended stability phase diagram model that takes into account all three effects and the effective damping measured independently using broadband ferromagnetic resonance technique enabled the determination of both STT and VCMA coefficients that are responsible for the FL magnetization switching.
Highlights
Magnetic tunnel junctions (MTJs) have become a basic building block for various types of spintronics devices, such as magnetic random access memory (MRAM) cells, magnetic field sensors and microwave generators or detectors[1]
We report on the perpendicular MTJ with a composite CoFeB/W/CoFeB FL8, 9 which is characterized by high perpendicular magnetic anisotropy and spin polarization resulting in up to 180% tunneling magnetoresistance (TMR) measured at room temperature and above 280% TMR at low temperature
The bottom Co/Pt super-lattices coupled by a thin Ru spacer are characterized by high perpendicular magnetic anisotropy (PMA)
Summary
Magnetic tunnel junctions (MTJs) have become a basic building block for various types of spintronics devices, such as magnetic random access memory (MRAM) cells, magnetic field sensors and microwave generators or detectors[1]. One of the key challenges for the commercial development of spin transfer torque (STT)-MRAM is to optimize perpendicular MTJ to withstand the temperature budget introduced at the back end of line CMOS fabrication process with temperatures up to 400 °C. To achieve this a precise design of the layer stack, taking into account all constituent layers as well as the properties and the treatment of the bottom electrode, has to be performed. An analytic model based on work by Bernert et al.[13] was extended to reproduce the experimental results
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