Abstract
In this paper, a design of low power m-sequence code generator is proposed. The efficiency of producing the code sequence within the region of sub-threshold voltage is investigated using 90nm technology and verified using the auto-correlation and eye diagram characterizations. A further method of power saving in addition to voltage reduction is carried out by scaling the technology node from 90 to 65nm. A comparison of power consumption and maximum attainable frequency between both technologies is performed. The ratio of power saving while using 65nm technology is ranging from 45% to 55% for the three different code lengths investigated.
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