Energy and area analysis of a floating-point unit in 15nm CMOS process technology

Abstract

The continuous increase in transistor density based on Moore's Law has led us to Complementary Metal-Oxide Semiconductor (CMOS) technologies beyond 45nm process node. These highly-scaled process technologies offer improved density as well as a reduction in nominal supply voltage. New challenges also arise, such as relative proportion of leakage power in standby mode. In this paper, we present an analysis regarding different aspects of 45nm and 15nm technologies, such as power consumption and cell area to compare these two technologies. For this purpose, an IEEE 754 Single Precision Floating-Point Unit implementation is analyzed based on 45nm and 15nm technologies. The results have shown that using the 15nm technology we can have 4 times less energy and 3-fold smaller footprint.