A Survey on Power Gating Techniques in Low Power VLSI Design

Abstract

The most effective technique to reduce dynamic power is the supply voltage reduction by technology scaling which reduces threshold voltage. Under deep submicron technology, reduction in threshold voltage increases leakage currents, gate tunneling currents and leakage power in standby mode. Most of the handheld devices have long standby mode cause leakage current contributing to leakage power dissipation. In this paper, various leakage power reductions, charge recycling techniques, data retention of memories. Various Power gating techniques are discussed in detail.