Abstract
Approximate or inexact computing has gained a significant amount of attention for error tolerant systems such as signal processing and image processing applications. In this paper, a comprehensive analysis and evaluation of multipliers realized using the existing approximate 4-2 compressors towards achieving low power has been presented. 8-bit Dadda multiplier has been chosen and the power consumption comparison has been performed. The exact multiplier has also been realized to enable the calculation of power savings for the approximate multipliers. An image compression algorithm using approximate multipliers has been implemented to analyze the operability of the approximate multipliers. Accuracy of the approximate multipliers has also been computed by means of Normalized Error Distance (NED) and PSNR. All the circuits are designed using 45nm CMOS process technology and simulations are carried out using Cadence® Virtuoso design tools.
Published Version
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