Transistor-Clamped Multilevel H-Bridge Inverter in Si and SiC Hybrid Configuration for High-Efficiency Photovoltaic Applications

Abstract

Using wide bandgap (WBG) devices has been a promising solution to improve the efficiency of power inverters for photovoltaic (PV) applications. However, for multilevel inverters, using WBG devices to improve the inverter efficiency can increase the system cost dramatically due to the high price of WBG devices in the present market as well as the large number of power devices typically required in multilevel inverter topologies. In this paper, a five-level transistor clamped H-bridge (TCHB) inverter will be further investigated. This inverter requires much lower number of semiconductor switches and fewer isolated dc sources than the conventional cascaded H-bridge inverter. To improve the inverter efficiency, semiconductor switches operating at carrier frequency will be configured by Silicon Carbide (SiC) devices to reduce the dominant switching losses, while the switches operating at fundamental output frequency (i.e., grid frequency) will be constituted by Silicon (Si) devices. As a result, both of the peak efficiency and California Energy Commission (CEC) efficiency of the TCHB inverter are significantly improved and dramatic system cost increase is avoided. In addition, due to the faster saturation characteristic of the IGBT devices, the large short-circuit current in SiC MOSFETs is constrained under the condition of load short-circuit faults. In other words, this proposed “SiC+Si” hybrid TCHB inverter can ride through a load short-circuit fault. Simulation and experimental results are presented to confirm the benefits of this proposed hybrid TCHB inverter.