Current balancing techniques of parallel-connected silicon carbide MOSFETs: A review

Abstract

Scientific studies have been published over the last decade in which several researchers have proposed numerous techniques for limiting the current unbalance between a number of discrete parallel Silicon Carbide (SiC) MOSFETs. This unbalance is unavoidable and should be limited in order to exploit all the advantages offered by SiC semiconductors over Si counterparts as far as possible. This effort aims to optimize the operation of converters in medium and high-power density applications. Such applications are converters for photovoltaic power generation, electric vehicles, high-power density motor drives, smart grids, solid-state transformers for distribution network, HVDC transmission, railway systems, etc. SiC MOSFET, as one of the Wide Band Gap (WBG) devices, has become increasingly popular in the aforementioned applications because of its superior characteristics and the increasing demands for higher efficiency and reliability, higher limits of power density, lower weight/volume packages and higher thermal operating limits of electric power conversion. However, these applications are characterized by high currents and therefore the parallelism of SiC MOSFETs is necessary either by paralleling a number of discrete SiC MOSFETs or by designing and building multi-chip SiC MOSFET power module. Consequently, these techniques increase the reliability and performance of SiC MOSFETs’ parallel operation by reducing conduction and switching losses, power losses and simultaneously achieving energy savings while reducing the environmental impact. In this paper techniques for suppressing the current imbalance which occurs between parallel-connected discrete SiC MOSFET are reviewed and presented. These techniques are analyzed, discussed and compared. The aim of this bibliographic review and comparative study is to highlight the techniques that combine low complexity and high efficiency in their implementation.