Trade-Off-Oriented Impedance Optimization of Chiplet-Based 2.5-D Integrated Circuits With a Hybrid MDP Algorithm for Noise Elimination

Abstract

Interposer and chiplet-based 2.5-D integrated circuit (IC) designs have become a new trend for block-level heterogeneous integration. In this paper, a new hybrid metaheuristic algorithm named Metropolis-based differential particle swarm optimization (MDP) is designed to jointly optimize the multiconstraints and impedance-based hybrid objective function of chiplet-based 2.5-D IC including interposers, chiplets, through-silicon via (TSV) arrays, bumps, and metal-insulator-metal (MIM) capacitors for simultaneous switch noise (SSN) reduction. Combined with the cascaded PDN assembly method, constraints on routing, delay and proximity distance between the entire system and an impedance-oriented function with multiple critical factors, a hybrid objective function with respect to the 2.5-D PDN is obtained. Integrating the advantages of multiple algorithms, a better hybrid MDP algorithm is designed to optimize the proposed key function. This method adopts the Metropolis rule to avoid the waste of the update mechanism for out-of-boundary particles. The placement, orientation of the chiplets, the on-interposer decoupling capacitor and the constraints of the 2.5-D system are co-optimized to find the optimal solution to eliminate the SSN. The overdesign of the system, different target impedance, different objective-oriented circuit optimization schemes and trade-offs in different constraints are also discussed carefully in this paper for 2.5-D ICs.