Introducing redundant TSV with low inductance for 3-D IC

Abstract

Three-dimensional integrated circuit (3-D IC) is created by vertically stacking and bonding multiple two-dimensional integrated circuits (2-D IC). In the process 3-D IC provides highly dense circuits with significantly more functionality in a relatively smaller footprint. Layers of 3-D IC are electrically interconnected using through silicon via (TSV). TSVs are used to transmit data, clock and power signals. However, yield for TSVs is lower than the conventional interconnects, hence their reliability is of a greater concern. Also, TSV are inductively limited than capacitive limited, which may lead to significant inductive-coupling. In this paper we explore the grouping of thinner TSVs to replace a thick TSV (with identical current carrying capability), which in turn provide redundant TSV paths and improved reliability. It is observed that the proposed structure not only provides redundant path but at the same time, it reduces the TSV inductance, which leads to Ldi/dt noise reduction. Closed form mathematical equations are derived to calculate RLC parasitic of grouped TSVs. To the best of our knowledge, this is the first work towards investigating the grouping of thin TSVs. Results show the reduction of inductance of up to 56% and provides redundant paths in case of TSV failures without extra design overhead at the expense of maximum 10% reduction in bandwidth.