Vertical Delay Modeling of Copper/Carbon Nanotube Composites in a Tapered through Silicon Via

Abstract

A model of copper and carbon nanotube (CNT) composite filled through silicon via (TSV) is developed to estimate signal delay of a novel interconnect, employed in 3D integrated circuit (IC) design. The main objective of 3D interconnect is to electrically connect two stacks of circuits and offer robust chip functionalities. The 3D integration scheme allows independent design of operational blocks in separate layers, that areelectrically integrated through conductive TSVs. The Cu/CNT composites filled TSV is seen as next generation interconnect and a delay model incorporating composite nature is beneficial in realizing novel 3D IC. The paper proposes a model derived from elmore delay method to estimate bidirectional vertical signal delay for Cu/CNT composites in a tapered TSV profile. The proposed model was applied for various proportions of Copper in Cu/CNT composites filled tapered TSV to study the impact of Cufilling ratio on the signal delay. The proposed delay model was verified for a Cu filled tapered TSV mentioned in the literature. In addition, the impact of tapered profile of TSV on vertical signal delay was investigated using the developed model. The model suggested that tapered sidewalls of vertical interconnect offers less signal delay as compared to cylindrical shape of TSV, however the disparity in bidirectional vertical signal delay increases with tapered profile. The developed delay model is recommended as auseful tool for 3D IC design.