Electrical modeling of copper/multiwalled carbon nanotubes for 3D IC applications

Abstract

Three dimensional (3D) interconnect is a solution for designing today's Integrated Circuits (ICs) in a view to achieve the ever growing consumer and market demands. The 3D interconnects in the form of copper filled Through Silicon Via (TSV) technology has offered significant advantages in adding more functionalities to the chip, keeping similar die size. With 3D interconnects, the designers can emphasize more on device placements and less on routing wires in the floor planning stage. The 3D TSVs has improved the performance of the chip via reduced RC delays, and lower energy as compared to a traditional planar interconnect design. Traditionally 3D TSV is composed of copper (Cu) filled in a high aspect ratio via within dielectric to electrically connect vertical stack of devices. A standardized damascene electroplating technique is used to fill copper in the TSV. Although the process is well studied and reliable results are found for System On Chip (SoC) applications, Cu exhibits electromigration and skin effect problems for high frequency applications. Alternately Carbon Nanotubes (CNTs) as interconnects have indicated high current carrying capacity and enhanced thermal performance. This paper focuses on the development of electrical models for Copper/Multi Walled Carbon Nanotube (Cu/MWNT) composites in tapered TSVs, which is different from Copper/Single Walled Carbon Nanotubes (Cu/SWNT) composites based 3D interconnects. The Cu/MWNT modeled results were further analyzed and compared with SWNT filled TSVs and Cu filled TSVs. In addition, a bidirectional vertical delay model is developed for Cu/MWNTs filled TSVs and the signal delay is analyzed for different proportions of Cu in the novel 3D interconnect. The modeled Cu/MWNT composite interconnects is considered beneficial for 3D IC package design.