Abstract
Evolvable Hardware (EHW) is a field of Evolutionary Computation (EC) started in the early 1990’s that includes a subfield of Evolvable Hardware Design and a subfield of Adaptive Hardware. Two methods of evolvable hardware design of a one-bit full adder are analyzed in this paper: first method is based on the well-known idea of gate-level design using a network of programmable gates, and the second method uses Verilog instructions coded in chromosomes represented as binary strings. Eventually, the two solutions were compared in terms of hardware resources and propagation times.
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