Abstract
To increase the speed of evolvable hardware, a complete on-chip evolvable hardware technique is adopted, where both hardware evaluation and evolutionary algorithm itself are configured on chip. At the same time, a multi-objective evolutionary algorithm based on Pareto dominance is proposed to satisfy and conciliate multiple objectives in many combinational circuits design. This method is applied to the design of a 1-bit full adder and its feasibility is validated by the result of the experiment. The data of result also shows that the speed of evolvable hardware is dramatically increased.
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