Abstract

Many IC design houses failed to be market leaders because they miss the market window due to timing closure problems. Compared to half‐micron designs, the amount of time spent on timing verification has greatly increased. Cell delays can be accurately estimated during logic synthesis. However, interconnect delays are unknown until the wire geometry is defined in physical design. Logic synthesis using the cell library models for interconnect delay estimates may be statistically accurate, but can not predict the delay of individual nets accurately. Delay estimates for individual nets (global nets, long wires, large fan‐outs, buses), which matter most for the critical paths can be inaccurate and cause a design failure. Inaccurate timing verification causes silicon failure in shipped products that results in the loss of millions of dollars spent designing a high‐performance product and potentially larger costs due to lost market share. Full‐chip, sign‐off verification with silicon‐accuracy will allow these problems to be discovered and fixed before tape‐out.

Highlights

  • The industry is on the brink of logic integrated circuits (ICs) crammed with over 100 million transistors

  • Cell delays can be accurately estimated during logic synthesis, interconnect delays are unknown until the wire geometry is defined in physical design

  • The synthesis tool employs inplace optimization (IPO)—changes the drive strength of cells based on interconnect delay estimates without altering the netlist structure

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Summary

INTRODUCTION

The industry is on the brink of logic integrated circuits (ICs) crammed with over 100 million transistors. Successful delivery of the complex ICs rests on three pillars of support They are superior electronic design automation (EDA) tools, advanced technology IC manufacturing, and powerful design flow methodology. The very deep sub-micron (VDSM) (below 0.25 mm) IC manufacturing technology, to produce the complex ICs today and in the future, has had a direct influence on both the EDA tools and design flow methodology. The timing inaccuracy results in a productivity gap, especially for VDSM ICs, in which both EDA tools and traditional design flows break as they cannot keep pace with the rapid IC technology advances. The future mission is to develop siliconaccurate timing verification tools and positioning the tools in design flow methodologies to close the productivity gap of VDSM ICs. Traditionally a dynamic simulator, at either the logic level or the circuit level, has been employed to verify the functionality and timing of an entire design or functional blocks within the design.

Process technology
Interconnect Delay Modeling Faced New Challenges for VDSM ICs
Pessimistic Timing Constraints Rendered a Difficult Delivery of VDSM ICs
Unintentional Clock Skew and Phase Delay Cause Circuit Malfunction
IR Drop Effect Creates Variations in Timing and Causes Silicon Failure
Timing Closure and Signal Integrity Faces New Challenges for VDSM IC
SPICE deck simulation
Timing Accuracy
Findings
CONCLUSION
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