APR-16: The Physical Design of a Reconfigurable Array Processor Chip

Abstract

In the physical chip design under the ultra-deep submicron (UDSM) process, interconnect delay, internal resistance drop (IR drop), and signal integrity (SI) has become the key factors affecting timing convergence and design cycle. This paper introduces a reconfigurable array processor architecture chip to solve the above problems. It discusses the requirements of the chip, the logic synthesis, and the physical design under the SMIC 55nm process in detail. First, four different timing optimization methods are employed to optimize the critical path that affects the timing, thus accelerating the execution time of the subsequent placement and routing. Secondly, the edge placement method based on data flow is adopted to reduce the interconnect length and delay of interconnection. Finally, the power network synthesis, placement, clock tree synthesis, and routing are completed. The results demonstrate that the working frequency can reach 320MHz. Meanwhile, the resource consumption is 80506 logic gates, and the chip area is 12mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> .