Layout-based logic decomposition for timing optimization

Abstract

As feature sizes shrink to deep sub-micron, the performance of VLSI chips becomes dominated by the interconnect delay. In a traditional top-down design flow, logic synthesis algorithms optimize gate area or delay without accurate interconnect delay because of lack of physical design information. Thus, the effectiveness of the optimization techniques is limited. We integrate logic synthesis and physical design into an iterative procedure for performance optimization. The logic synthesis process can optimize circuit delay based on accurate interconnect delay information extracted from the physical design. The physical design tools can refine the layout incrementally with the engineering change information and changed netlist passed from the logic synthesis process. In this thesis, we integrate logic decomposition, gate sizing and buffer insertion to work together to improve the circuit speed. Experimental results on a set of benchmark circuits show that the techniques are indeed effective.