Theoretical model of interface trap density using the spread of the differential capacitance characteristics in scanning capacitance microscopy measurements

Abstract

In this letter, we propose a theoretical model for the calculation of interface trap density (Dit) in a metal-oxide-semiconductor structure using data from scanning capacitance microscopy (SCM) measurements. The model is based on the correlation of Dit with the change in the full width at half maximum of the SCM differential capacitance (dC∕dV) characteristics. The good agreement between the calculated Dit values from the SCM theoretical model and the experimental midgap Dit values obtained from conductance measurements shows the validity of the proposed model. The model opens up possibilities for obtaining the spatial distribution (with nanometers resolution) of interfacial traps on a device using SCM measurements.