Spatial distribution of interface trap density in strained channel transistors using the spread of the differential capacitance characteristics in scanning capacitance microscopy measurements

Abstract

In this letter, the authors obtain, with nanometer spatial resolution, the local spatial distribution of interface trap density (Dit) at the gate oxide-substrate interface across the channel region of a transistor with silicon germanium source/drain (S/D) stressors. The Dit values were extracted using a theoretical model which is based on the correlation of Dit with the change in the full width at half maximum of the scanning capacitance microscopy differential capacitance characteristics. Results show that Dit increases with spatial location, measured from the center of the channel, towards the S/D regions of the strained channel transistor. The large value of Dit near the S/D regions is possibly due to germanium diffusion into the channel region and other resulting structural defects.