Abstract

This paper investigates the possibility of using Field-Programmable Gate Arrays (Fpgas) as reconfigurable co-processors for workstations to produce moderate speedups for most tasks in the design process, resulting in a worthwhile overall design process speedup at low cost and allowing algorithm upgrades with no hardware modification. The use of Fpgas as hardware accelerators is reviewed and then achievable speedups are predicted for logic simulation and VLSI design rule checking tasks for various Fpga co-processor arrangements.

Highlights

  • Many special hardware acceleration engines have been proposed or built ], with significant speedups over software

  • The VLSI design process is characterized by many computer-intensive stages that are quite different in nature

  • The development of static RAM based FieldProgrammable Gate Arrays means that reconfigurable co-processors can be realized that could accommodate the diversity and dynamic nature of design automation tasks

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Summary

Introduction

Many special hardware acceleration engines have been proposed or built ], with significant speedups over software. The VLSI design process is characterized by many computer-intensive stages that are quite different in nature. The continual development of algorithms counts against hardwired accelerators. The development of static RAM based FieldProgrammable Gate Arrays means that reconfigurable co-processors can be realized that could accommodate the diversity and dynamic nature of design automation tasks. The speedup achieved for any one task will be less than that for a complex dedicated hardware accelerator but, applied to speed up tasks throughout the design process, it may provide a substantial benefit for a very low hardware cost. Algorithms could be upgraded without hardware modification.

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