Radar Pulse on Pulse Identification Algorithm Hardware Acceleration Performance Analysis

Abstract

The performance in radar receiver signal processing is a critical factor in identifying radar pulses. The use of field-programmable gate arrays (FPGA) in hardware acceleration provides multiple advantages in radar signal processing. High-level synthesis (HLS) tools enable systems developed in high-level languages, such as C, flexibility in conversion to a register-transfer level (RTL) design. A direct HLS translation for an FPGA target may not always improve performance, and analysis is compelling in systems where speed and performance are crucial. System on a Chip (SoC) FPGAs includes a processing system (PS) and programmable logic (PL) architectures on a single device. The performance between high-level language designs executed on the PS and HLS adaption implemented on the PL can be directly analyzed. This paper presents the performance comparisons of a Python and HLS versions of a previous work radar pulse on pulse identification algorithm implemented on an SoC FPGA.