The thermal stress analysis in 3D IC integration with TSV interposer

Abstract

The 3D IC integration technology may achieve high performance, better reliability in electronic applications. Since the through silicon via (TSV) provides the key connection in 3D IC integration, the reliability issues of TSV are very important. In the TSV architecture, the electroplating copper is filled in the TSV. As the difference of coefficient of thermal expansion (CTE) between silicon and copper is more than 10 ppm/K, the thermal stress will be critical when the thermal load is applied. In this study, the typical 3D IC integration device with TSV interposer was investigated. Taking the advantage of the symmetric, 1/8 model was built in ANSYS according to the device design geometry. The submodel method and sector model were verified and used to overcome the huge computational cost due to meshing the amount of micro-sizes TSV. The thermal stress distribution in the whole model and TSVs was demonstrated by 1/8 symmetric model and interposer submodel. Using the submodel and sector model, the two TSV parameters, the diameter and the pitch of TSV, were selected to perform parametric study. The critical location of TSV and TSV pitch design rule were discussed on the basis of the analysis results.