The relationship between the single event upset and the order of sensitive transistors in flip-flop layout

Abstract

Traditionally, it is believed that only reverse biased PN junctions can collect ionized electron-hole pairs. Therefore, only the drain of the transistor in the off-state can be considered as a sensitive node, which is easy to absorb charge and cause upset. This paper finds that on-state transistors can also become sensitive nodes. This paper studies the relationship between SEU and the order of transistors in the flip-flop layout. It is found that the adjacent placement of on-state sensitive transistors can promote the occurrence of SEU, and a targeted hardened plan is proposed. The results of this paper are helpful for the design of the radiation-resistant layout of the flip-flop.