The electrical and physical analysis of Pt gate/Al2O3/p-Si (100) with dual high-k gate oxide thickness for deep submicron complementary metal-oxide-semiconductor device with low power and high reliability

Abstract

In order to examine the electrical and physical properties of Al2O3 layers with dual thickness on a chip, Pt gate/Al2O3 with dual thickness/p-type Si (100) samples were fabricated using atomic-layer deposition, separation photolithography, and 100:1 HF wet etching to remove the first Al2O3 layer. Dual metal-oxide-semiconductor (MOS) capacitors with thin (physical thickness, ∼4.5 nm, equivalent oxide thicknesses (EOT): 2.8 nm) and thick (physical thickness, ∼8.2 nm, EOT: 4.3 nm) Al2O3 layers showed a good leakage current density of −5.4×10−6 A/cm2 and −2.5×10−9 A/cm2 at −1 V, respectively; good reliability characteristics as a result of the good surface roughness; low capacitance versus voltage measurements (C-V) hysteresis; and a good interface state density (∼7×1010 cm−2eV−1 near the midgap) as a result of pre-rapid thermal annealing (pre-RTA) after depositing the Al2O3 layer compared with the single MOS capacitors without the pre-RTA. These results suggest that dual Al2O3 layers using the dual gate oxide (DGOX) process can be used for the simultaneous integration of the low power transistors with a thin Al2O3 layer and high reliability regions with a thick Al2O3 layer.