Testing techniques for resistive-open defects in future CMOS technologies

Abstract

In this paper, we investigate the effectiveness of different testing techniques in detecting resistive-open defects for adder circuits implemented using current and future CMOS technologies down to 22nm. We take into consideration the wide process variations associated with such technologies. The first method is based on monitoring various characteristics of the transient power supply and ground currents (i <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DDT</sub> ) while the second method relies on measuring the propagation delay from the primary inputs to primary outputs. The transistor models are acquired from the Predictive Technology Model website (PTM) and the percentage variations for technology parameters are obtained from the existing literature. Results show the effectiveness of the i <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DDT</sub> methods for small circuits. However, the capability of the method declines for larger circuits. The delay test proves to be very effective in all cases.