Transient current testing for future CMOS technologies

Abstract

In this paper we investigate the effectiveness of i <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DDT</sub> -based testing in detecting resistive open defects for future CMOS technologies down to 22 nm taking into consideration the wide process variations associated with such technologies. The SPICE parameters that we use for such advanced models are taken from the predictive technology model (PTM) and the ranges of process variations are taken from the literature provided by industry and researchers in the field. We target resistive open defects because they are hard to detect by traditional voltage testing techniques and by IDDQ testing. Simulations results show that i <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DDT</sub> -based testing provides a good premise for detecting hard-to-catch defects such as resistive opens in future CMOS technologies.