Transient current and delay analysis for resistive-open defects in future 16 nm CMOS circuits

Abstract

In this paper, we investigate various testing techniques for detecting resistive-open defects in 16 nm CMOS technology taking into consideration the wide process variations associated with such a technology. We will use two techniques: the first is the iDDT method that detects unexpected transient power supply and ground currents by looking at their peak values or by finding the RMS value of their wavelet transform. The second method consists of measuring the propagation delay from the primary inputs to the circuit outputs. The simulation parameters that we use for the transistor models are taken from Predictive Technology Model (PTM) and the process variation of each parameter is obtained from the existing literature. Results show that the peak i DDT and wavelet techniques provide an acceptable detection percentage, while the delay test proves to be very effective in detecting resistive-open defects even in the case of extreme process variations.