The effectiveness of delay and IDDT tests in detecting resistive open defects for nanometer CMOS adder circuits

Abstract

In this paper we evaluate the effectiveness of different testing schemes in detecting resistive-open defects in adder circuits implemented using different CMOS technologies (45 nm, 32 nm, 22 nm and 16 nm). We assess the detection capabilities of four testing techniques taking into consideration the wide process variations associated with the different nanometer technologies. The first three techniques are based on the transient supply current, i <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DDT</sub> , and the fourth technique is based on delay testing. The first i <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DDT</sub> method uses the RMS value of the wavelet transform of the transient power supply or ground currents. The second one uses the normalized RMS value of the wavelet transform. The third one uses the peak value of i <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DDT</sub> . The fourth technique measures the primary input-to-output delay. The experimental results show that the delay test is the most effective among all tests. The i <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DDT</sub> test with normalized RMS value of wavelet transform comes second. The other two tests were less effective than the first two, especially in the case of smaller technologies (22 and 16 nm).