Testing for stuck-at-faults in multiple output MOS combinational circuits

Abstract

Abstract Recently, we have introduced a comprehensive model for detecting single and multiple faults for MOS combinational circuits based on the logic transistor function concept. In this paper, we extend our previous work to cover MOS combinational circuits that have multiple output lines. A new algorithm is developed which is used to generate test vectors that are capable of detecting single and multiple stuck faults in multiple output MOS combinational circuits. We also introduce a new concept where all the transistors in a specific circuit are realized into a number of transistor sets which alleviates the analysis and planning of a test strategy that accommodates a particular test requirement, i.e. detecting a certain transistor fault occurrence, or fits particular test restrictions, i.e. output line limitation. The advantages of this concept in design for testability is outlined. The relationship of fault coverage and output lines is also introduced and analysed.