A row-based FPGA for single and multiple stuck-at fault detection

Abstract

This paper presents a practical and low cost design-for-testability (DFT) scheme for the row-based field programmable gate array (FPGA) which is widely used for rapid prototyping, hardware verification/emulation of VLSI chips and manufacturing of complex digital systems. A new module is introduced for the DFT of the FPGA. The proposed DFT scheme permits the uncommitted FPGA to be tested using a set of constant cardinality (C-testability) for single and multiple stuck-at fault detection, while reducing the number of required primary test pins to only one. The number of tests for the FPGA is still 8+n/sub f/ (where n/sub f/ is the number of sequential modules in a row of the array), but only one primary pin and a small amount of testing circuitry are now required. This paper also modifies the single fault test set to accomplish multiple fault detection under two multiple fault models: the multiple fault single module (MFSM) and the single fault multiple module (SFMM) models. It is shown that by appropriately changing the don't care entries in the vectors of the test set for single fault detection, 100% and nearly 100% fault coverages can be achieved under the MFSM and SFMM models respectively.