Abstract
The paper describes the research results in the field of ternary codes construction focused on the use of checkable digital devices and systems and their diagnostic support in the synthesis tasks. The article provides a method for constructing a ternary sum code, which is analogous to the classical binary Berger code. The article identifies the previously unknown properties of error detection by the ternary sum code in the case of their occurrence only in the data vectors with the faultlessness of check bits. This task is relevant in practical applications where the bits of the check and data vectors are calculated physically by different devices. In addition, a comparison of binary and ternary sum codes is carried out. The article shows that the share of undetectable errors with the d multiplicity from the total number of errors with this multiplicity in the sum codes is a constant value and does not depend on the length of the data vector. This property is inherent in both binary and ternary sum codes.
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