Sum Codes of Weighted Data Bits for Objectives of Automation Logical Devices Technical Diagnostics

Abstract

The properties of codes with the summation of weighted data bits regarding detection of errors in the data vectors are researched by the authors. Such a problem arises if the sum code is used as some basis for the technical diagnostics system, for example, the concurrent error-detection system of logical devices of automation and computing hardware. Characteristics of error detection ability determine the synthesis strategy of technical diagnostics equipment in the fault detection systems via one or another sum code. A brief review of the use of classical and weighted sum codes for the purpose of discrete systems technical diagnostics problem solving is given in the article. Classification of sum codes is presented. The error detection characteristics in data vectors via weighted sum codes according to types (unidirectional, symmetrical and asymmetrical ones) and multiplicities are analyzed in detail. It has been proved that weighted sum codes, which do not use the deduction operation on a predetermined module during plotting, have the property of identifying any unidirectional distortions in the data vectors. Besides, it has been proved that weighted sum codes cannot have a uniform distribution of data vectors between all check vectors, which means that it is impossible to plot a weighted sum code with a theoretical minimum of the total number of undetectable errors. A method for implementing weighted code generators with summation, based on the use of standard adders and half adders' circuits, is presented. This approach is translated to the use of multiplexers being the part of the structures of modern programmable logic integrated circuits and widely used for development of modern automation systems and computing equipment.