Abstract
Test generation for sequential VLSI circuits has remained a difficult problem to solve. The difficulty arises because of reasoning about temporal behavior of sequential circuits. We use temporal logic to model digital circuits. Temporal Logic can model circuits hierarchically. A set of heuristics is given to aid during test generation. A hierarchical test generation algorithm is proposed.
Highlights
Test generation for sequential VLSI circuits has remained a difficult problem to solve
This theoretical result is supported by recent advances in test generation algorithms for combinational logic with impressive results reported on benchmark circuits [21]
Our goal is to develop an efficient scheme for test generation for sequential circuits
Summary
Igital circuits are tested during manufacture and field operation by application of a sequence of test vectors. While the test generation problem is NP-complete even for combinational circuits [11], there is some evidence that the average-time complexity may not be exponential [24]. This theoretical result is supported by recent advances in test generation algorithms for combinational logic with impressive results reported on benchmark circuits [21]. To accelerate the search process implied by such rea- Though the test generation problem for combisoning Both synchronous and asynchronous circuits national circuits is NP complete, there are many alcan be represented by our formalism. Programs have been developed recently [2, 22, 23]
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