Synthesis optimization by redesigning FPGA architecture for area-speed optimization

Abstract

In FPGAs the data path computations are all optimized for delay and logical depth. Still current FPGAs support modification in the existing internal scheme to provide higher performance computations. This paper presents how an optimization can be achieved by redesigning the FPGA architecture of carry propagation stage. The data computation path is modified with two different structures to reduce the delay aspect and the number of logic levels. The module functionality are described using Verilog HDL and performance issues like slice utilized, simulation time, percentage of logic utilization, level of logic are analyzed at 90 nm process technology using SPARTAN6 XC6SLX150 XILINX ISE12.1 tool.