Performance Enhancement Through Optimization in FPGA Synthesis: Constraint Specific Approach

Abstract

Circuit synthesis denotes the automated generation of logic networks from behavioral descriptions at an arbitrary level. Synthesis is becoming a key issue in VLSI design for efficient and flexible usage of cell and component. The architectural synthesis involves resource allocation, resource binding, and scheduling tasks. As the capacity of FPGAs increases, synthesis tools and efficient synthesis methods for targeted device become more significant to efficiently exploit the resources and logic capacity. This paper explores a design solution and synthesis optimization constraints for targeted FPGA device. The issue focuses on: the synthesis optimization for various modeling approaches; synthesizer producing sub optimal results for setting the target constraints too high; how an inefficient coding style can adversely impact synthesis and simulation, resulting in slow circuits. All the design solutions are elucidated with appropriate example. The module functionality are described using Verilog HDL and performance issues like slice utilized, simulation time, percentage of logic utilization, level of logic are analyzed at 90 nm process technology using SPARTAN6 XC6SLX150 XILINX ISE12.1 tool.