Analysis on Impact of Behavioral Modeling in Performance of Synthesis Process

Abstract

Cell-based design techniques, such as standard-cells and FPGAs, together with versatile hardware synthesis are rudiments for a high productivity in ASIC design. Several monumental changes have occurred in the design structure and execution of electronics principles. In the design process the functionality is defined through Hardware Description Language. The principal feature of a HDL is that it contains the capability to describe the function of hardware independent of implementation. Generally HDL coding styles can have a significant effect on the quality of results and also has the greatest effect on the performance of any event-driven simulator, and is often obvious. Synthesis tools optimize HDL code for both logic utilization and performance of an intended design. This paper focuses how an inefficient coding style can adversely impact synthesis and simulation, resulting in slow circuits, and rectification method to balance between the quality of the end hardware and optimized coding style that boost performance issues. The module functionality are described using Verilog HDL and performance issues like slice utilized, simulation time, percentage of logic utilization, level of logic are analyzed at 90 nm process technology using SPARTAN6 XC6SLX150 XILINX ISE12.1 tool.