Performance enhancement for variable block optimization in FGPA synthesis process

Abstract

Field Programmable Gate Arrays (FPGAs) is a general-purpose, multi-level programmable logic device which allows perfect customization of the hardware at an attractive price even in low quantities. Modern FPGAs became viable ASIC replacement because of very expensive fabrication process and time consuming test process. Unfortunately, the amount of reconfigurable resources is fixed and limited. While using the resources as well the logic implemented needs optimizations in order to meet the desired constraints. As the capacity of FPGAs increases, synthesis tools and efficient synthesis methods for target device become more significant to efficiently exploit the logic capacity. The synthesis tool provides a variety of design constraints which essentially helps the designer to meet the design goal such as area and speed to obtain the best implementation. This paper presents the implementation of modified ripple carry adder with various block optimizations for speed and area constraints. This modified structure produces better optimized output when compare to conventional ripple carry adder and parallel prefix adders like brent kung, Sklansky, Kogge-Stone etc. The module functionality are described using Verilog HDL and performance issues like slice utilized, simulation time, percentage of logic utilization, level of logic are analyzed at 90 nm process technology using SPARTAN6 XC6SLX150 XILINX ISE12.1 tool.