Synthesis-for-Testability Watermarking for Field Authentication of VLSI Intellectual Property

Abstract

Most VLSI watermarking techniques do not allow different authorships of multiple Intellectual Property (IP) cores to be detected directly in the field after the IPs have been integrated, fabricated and packaged into chip. Watermark inserted at the design-for-testability (DfT) stage makes its direct detection after chip packaging possible, but it protects only the downstream placement-and-routing design, and is vulnerable to removal attack as the test logic is independent of the functional logic. In this paper, we propose a publicly detectable watermarking scheme to bridge the gap between IP protection and IP management. The design is watermarked by means of synthesis-for-testability (SfT), where the test and functional logics of the IP are merged and synthesized together without using scannable flip-flops. Watermarked constraints are imposed on the scan chain ordering problem in the SfT process so that ownership of the embedded IP can be publicly identified by lawful IP providers, buyers and consumers by injecting a specific test vector in the field. The overhead due to the watermark insertion is minimized by a nearest neighbor search algorithm for flip-flop reordering. As the scan function is an integral part of the design in the synthesis process of the IP creation, the watermark is harder to be removed relative to other scan chain watermarking schemes whose test circuits are logically independent of the IP functionality. To deter and track IP fraudulence by the licensees, a provable mechanism is proposed to enable multiple authorships of different IP cores in a single chip to be publicly authenticated in the field. Experiments performed with ISCAS89 and LGSyn93 benchmark circuits show that the proposed watermarked designs have low design overheads, and the probabilities of coincidence and removal reduce rapidly with increased watermark and scan chain length.