Abstract
With the development of research on IEEE Std1500, IP (Intellectual Property) cores compatible with IEEE Std1500 are more and more. IEEE Std1500 provides wrapper architecture and TAM (Test Access Mechanism) for DFT (Design for Testability) of IP cores. So, the design of TAM becomes an important part of DFT for IP cores. Familiar TAM is introduced first, and then according to the characters of wrapper architecture, a TAM design based on bus is put forward. At last, TAM controller design for configurations of TAM is provided.
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