A System-level Mixed DFT-TAM Structure For SoC Design

Abstract

With the increasing complexity and chip scale of SoC, the test problem is becoming more difficult and important. Adding DFT (design for testability) in SoC design period has become the main method for solving the test problem. Based on analyzing some common DFT structures such as Fscan-Bscan, Fscan-Tbus, and the standard for embedded core test (SECT) IEEE P1500, a system-level mixed DFT-TAM (test access mechanism) structure has been presented in this paper. In this structure, different DFT methods are applied in different characteristic IP (intellectual property) cores to pursue the reasonable testing cost, then, a more flexible TAM is built in the system level for achieving every IP core test and testing the connection faults between two IP cores. By some experiments with the programmable video add data (VAD) SoC introduced in this paper, the higher fault coverage and lower test cost could be gotten