Abstract
A low-cost test solution for core-based system-on-a-chip (SoC) comprises of test access mechanism (TAM) design – for facilitating access to the embedded cores – and the use of test data compression (TDC) methods – for reducing test resources. While most previous work has considered TAM design and TDC independently, this work analyzes the interrelations between the two, outlining that unless compression characteristics are integrated in the TAM design, test resource penalties may be incurred. This is due to the dependency of some TDC methods on test bus width and care bit density, both of which are related to test time, and hence to TAM design. Therefore, this paper analyzes the interactions between TDC and TAM, and highlights the compression characteristics which need to be considered in compression-driven TAM solutions for reducing test resource penalties. Furthermore, it also shows how an existing TAM design method can be enhanced toward a compression-driven solution.
Published Version
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