Test control of TAM-bus: a solution for testing SoC

Abstract

The SoC (system-on-chip) based on reusable embedded IP (Intellectual Property) introduces new challenges for the test, since the SoC integrator may not know the implementation of the IP cores that are usually embedded in chip deeply. IEEE P1500 standard for embedded core test (SECT) is a standard-under-development that aims at improving ease of testing SoC. The SECT standardizes the core wrapper and the core test language (CTL), and leaves the design of test access mechanism (TAM) to the SoC integrator. The TAM-bus we proposed is a P1500 compliant TAM. This paper describes the control of TAM-bus. With a novel interface to the chip level JTAG test access port (TAP), the TAM control module can provide the control of the TAM and wrappers. The final test architecture is flexible and configurable. The test architecture we presented has been implemented in an industry SoC. The test coverage remains 99.40%. The hardware overhead increases only 0.17% due to the TAM-bus and the TAM controller. The experiment results demonstrate that the test architecture can offer the solution for testing SoC.