Abstract
A surface potential-based polycrystalline silicon thin-film transistor (poly-Si TFT) model is proposed. Surface and grain boundary (GB) potentials are calculated by solving one-dimensional Poisson equations in both perpendicular and lateral directions to a poly-Si surface. A drain current model considers composite mobility to describe conductivities at both GB and intragrain, GB-induced mobility modulation, hot carrier effect, gate-induced drain leakage, and trap-dependent generation current. A capacitance model is derived from physically partitioned terminal charges and coupled to a drain current behavior. Furthermore, the poly-Si TFT model incorporates external resistances to express lightly doped drain structure and internal resistances to express non-quasi-static effects. Solving the Poisson equations not only allows for the accurate simulations of drain current and capacitance, but also well reproduces the dependence of TFT characteristics on grain size, GB trap density, and temperature. This poly-Si TFT model is successfully implemented into a circuit simulator and verified by ring-oscillator simulation. The good agreements with the measurements of both static and dynamic characteristics confirm the validity of the model.
Published Version
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