Abstract
This paper presents a surface potential based poly-Si thin-film transistor (SPT) model for SPICE which is formulated with both surface and grain boundary (GB) potentials calculated by Poisson equations. The drain current model includes GB induced mobility modulation, hot carrier effect, gate induced drain leakage, and trap dependent thermal leakage. The capacitance model is derived from physically partitioned charges. The SPT model has succeeded in simulating device performances with good accuracy.
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