Investigation and Modeling of Z-Interference in Poly-Si Channel-Based 3-D NAND Flash Memories

Abstract

In this article, the Z-interference in 3-D charge trap nitride (CTN) NAND flash memory is investigated using technology computer-aided design (TCAD) simulation. In 3-D CTN NAND flash memory, Z-interference is caused by the neighbor word line (WL) programming. When a neighbor WL is programed, nitride layer-induced barrier enhancement (NIBE) and charge spreading effects in the nitride layer cause a threshold voltage (<inline-formula> <tex-math notation="LaTeX">${V}_{t}$ </tex-math></inline-formula>) shift in the victim WL. Also, the victim WL program state dependency of Z-interference caused by the charge spreading effect is investigated. In monocrystalline Si channel, there is a program sequence dependency due to the drain bias-induced barrier lowering (DIBL) effect. However, poly-Si channel has different characteristics because of grain boundaries. Therefore, Z-interference due to poly-Si grain boundary (GB) trap position randomness and GB trap density variation is analyzed. Finally, Z-interference is modeled using Simulation Program with Integrated Circuit Emphasis (SPICE), and the <inline-formula> <tex-math notation="LaTeX">${V}_{t}$ </tex-math></inline-formula> distribution according to the Z-interference is modeled using a Monte Carlo simulation.