Study on Transmitter with Stacking-MOS Structure of Interface Circuits for Cross-Domain CDM ESD Protection

Abstract

With the development of ICs toward system-on-chip (SoC) applications, complex power domains are inevitable in modern ICs. In addition, the fabricated transistors with thinner gate oxide for high-speed operation cause the ICs sensitive to charged-device model (CDM) ESD events, especially under cross-domain ESD stresses. During CDM stress across separated power domains, the whole-chip ESD protection can be traditionally established by power-rail ESD clamp circuits with the bi-directional diodes to conduct ESD currents away from the interface circuits. Some additional local ESD clamp designs were used to further reduce transient overstress voltages on the interface circuits across separated power domains. However, to achieve better integration in circuit-level design, interface circuits were deserved to be optimized for better area efficiency and cross-domain ESD robustness. Thus, the design and improvement of interface circuits became critical solution to on-chip CDM ESD protection for SoC integration. In this work, stacking-MOS structures with different gate connections have been implemented at the transmitter (TX) of interface circuits for investigating their cross-domain CDM ESD robustness. The experiment results on the silicon chip fabricated in a 0.18-μm 1.8-V CMOS process have compared the CDM levels among the interface test circuits with different transmitter circuits. Finally, the CDM failure on the interface circuit was discovered by electrical and physical failure analysis. The delayer SEM results presented the gate-oxide damage only in the receiver (RX) of the interface circuit after cross-domain CDM stresses.