Study of chip stack process and electrical property for 3D-LSI

Abstract

As for present electronic equipment, a further advanced functionalization (high speed and large capacity) is requested with the miniaturization and energy-saving. Especially, in portable equipment that supports IoT, by demanding making to high performance further, CPU of portable equipment approaches the performance of PC. Moreover, PC is more high-speed and high performance. A rapid performance gain of LSI is indispensable for these achievements. However, it becomes insufficient only by promoting the technology of making to minuteness of LSI wiring according to Moore's law. So, it is thought that becoming a key technology that solves the problem is three dimensional LSI chip mounting technology. Three dimension mounting technology is a technology that connects an upper and lower chip by metallic wiring that penetrates in Si that is called TSV(Through Silicon Via), and accumulates the chip. The wiring distance of between chips is shortened by these three dimension mounting technologies, and the function in the chip can be integrated in a high density. As a result, the achievement of high performance LSI(3D-LSI) that rapidly improves the performance for each mounting area becomes possible. We are examining the state and the electrical specification of the mounting condition and the joint part to connect the chip that forms TSV to the substrate with which the solder bump is formed in the chip stacking process that is the elemental technology of the mounting above-mentioned three dimensional technologies. In this study, the stacking process of the chip is examined, and it reports on the evaluation result of the electrical specification after it stacked. The stacked chip was made for a trial purpose by using the thinned chip of 100μm with TSV of 10μm diameter was formed. After mounting the first layer in Face to Face on silicon interposer, the stacking evaluation sample becomes a structure to connect the second layer with Face to Back for TSV in the back side of the first layer. The examined chip stacking process is as follows. First, after the chip had been mounted by the thermo compression bonding on silicon interposer, it connected it by the reflow because of the reduction atmosphere. Bonding Pressure, the heating temperature, time, and connected terminal structure were optimized, the sample to be able to do electrical continuity check was obtained. Right or wrong of the connection was confirmed by the resistive measurement by daisy chain. Next, the relation between the frequency and S parameter was measured with the network analyzer as a baseline assessment of the electrical property of the stacked by two layers. As a result, the linear relationship was admitted in the wiring route including TSV for the bump, the number of TSV, and the loss of transmission. Moreover, it has been understood that the difference between individuals of the transmission property of the wiring route is much smaller than two or more result of a measurements. As a result, it was shown that it was the stacking process where a steady characteristic was obtained.