Structures and Materials of System-in-Package: A Review

Abstract

Background: As a new type of advanced packaging and system integration technology, System- in-Package (SiP) can realize the miniaturization and multi-functionalization of electronic products and is listed as an important direction of development by International Technology Roadmap for Semiconductors (ITRS). Objective: This paper mainly introduces and discusses recent academic research and patents on package structure and packaging materials. Additionally, the trend of development is described. Methods: Firstly, we analyze and summarize the challenges and existing problems in SiP. Then the corresponding solutions are introduced with respect to packaging structure and packaging materials. Finally, the research status of SIP and some patents in these aspects are reviewed. Results: In order to increase the density of internal components, SiP products need to use a stacked structure. The causes of different performance in SiP products are: 1) the stress concentration and bonding quality problems caused by the chip stack structure; 2) the warpage and package thickness problems caused by the package stack; 3) thermal conductivity of materials and thermal mismatch between materials; and 4) dielectric properties and thermomechanical reliability of materials. The following solutions are summarized: 1) structural optimization of chip stacking and packaging stacking; 2) application of new packaging technology; 3) optimization of packaging materials; 4) and improvement of packaging material processing technology. Conclusion: With the study of packaging structure and packaging materials, SiP can meet the requirements of the semiconductor industry and have great future prospects.