Research on the stress in stacked chip packages

Abstract

Stacked chip packaging (3D packaging) is an effective method to increase the density of electronic packaging, due to the packaging density on an single chip has reached the limit of current packaging process. In stacked chip packaging system, additional chips are implemented on a single chip in the third dimension, thus multiply enhance the density of electronic packaging, while the packaging size in the plane remains almost the same. Comparing to normal 2D packaging, stacked packaging needs excess process to bond the added chips to the first-layer chip or the substrate. Two effective approaches are used to bond the stacked chips: one is to flip-chip bond the second chip to the pads on the back of the first-layer chip with through-silicon-vias (TSVs); the other is to bond the stacked chip to the first-layer chip with die attachment adhesive. In these processes, chips and substrates experience certain thermal procedures, and thermal stress is induced in the stacked chips. This stress may heavily affect the performance of devices and the reliability of the packaging system. In this study, silicon piezoresistive stress sensor chips are used to measure the stress distribution in stacked packaging system. Die attachment adhesive is used to achieve the 3D stacked packaging, and different stacked modes are utilized to complete the packaging process. The effect of chip size, stacked layers, stacked mode and underfill are studied, and the stress in both top chip and bottom chip are measured.